Present Chemical Vapor Deposition Equipment consists of a single or multiple chambers, gas inlets, gas outlets, vacuum pumps and transfer load-lock systems for inserting, for example, semiconductor wafers into the chamber. Prior art examples of Chemical vapor Deposition Equipment is described in U.S. Pat. No. 5,298,452 by B. S. Meyerson which issued on Mar. 29, 1994 which shows an Ultra High Vacuum Chemical Vapor Deposition (UHV-CVD) reactor with a vacuum loading apparatus.
An example of a cluster CVD system which is for single wafer processing with preheating and uniform temperature control is described in U.S. Pat. No. 5,259,881 by Edwards et al. which issued on Nov. 9, 1993.
In the growth of Si structures or Si/SiGe heterostructures via UHV-CVD processing, a critical step and requirement before loading wafers into the UHV-CVD equipment is to perform a dip of each Si containing wafer into HF acid to remove the native oxide from the wafer surface and to passivate the Si bonds at the surface with hydrogen. Si containing wafers after being dipped in HF acid are loaded into a vacuum loading apparatus of a CVD reactor and then inserted into the CVD reactor. This particular ex-situ HF cleaning procedure without a water rinse is a hazardous practice to be performed manually under a chemical hood and moreover, for patterned wafers, often there is residual HF liquid left on the wafer surface which would require additional N.sub.2 blowing of the residual HF off the wafer. Blowing residual liquid HF is an extremely hazardous manual process. Presently, this HF-dip is not an industry acceptable process and weakens the acceptance of the UHV-CVD processing technique for doing low temperature epitaxy in the semiconductor manufacturing industry.
Another key issue related to making high performance Si and/or Si/SiGe Metal Oxide Silicon (MOS) field effect transistor (FET) structures and/or Complementary Metal Oxide Silicon (CMOS) is the requirement for a very high quality gate dielectric and a gate electrode stack as described in U.S. Pat. No. 5,534,713 by K. Ismail et al. which issued Jul. 9, 1996. This patent describes a gate dielectric of an ultra-thin SiO.sub.2 layer with a thickness from 1 nm to 5 nm. The gate electrode is a heavily doped polysilicon structure.